Comparison between CISC and RISC Architectures

   Complex Instruction Set Computer

v Control unit is designed through software approach

v Micro-program is designed for each instruction

v Each micro-operation is performed by a micro-instruction

v Typically have small set of registers

v More access to memory

v More addressing modes involved

v Instruction execution in multiple T-states

v Introduction of new instruction is comparatively easier

v Error rectification is easier

v Instruction set is large and complex

v Speed slower than RISC counterpart

v Example: All the 80x86 machines prior to Pentium

v Used in Home Desktop, Low-end applications

Reduced Instruction Set Computer

v Control unit is designed through hardware approach

v Micro-circuit is designed for each instruction

v Typically have large set of registers

v Reduced access to memory

v Limited addressing modes involved

v Usually instruction execution in single T-state (clock cycle)

v Makes efficient use of Pipe lining

v Introduction of new instruction is cumbersome

v Error rectification is very difficult

v Instruction set is small and simple

v Speed is faster than CISC counterpart

v Example: SUN SPARC, ULTRA SPARC

v Used in speed critical, server, High-end applications.

Architectural Characteristics	CISC	RISC
	Complex Instruction Set Computer	Reduced Instruction Set Computer
Instruction Set Size	Large Set of Instructions	Small Set of Instructions
Instruction Formats	Variable Formats(16-64 bits per Instruction)	Fixed (32 bits) Instructions & mostly register based.
Addressing Modes	12-24	Limited to 3-5
General Purpose Registers & Cache Design	8-24 General Purpose Registers,mostly with a unified cache for instructions & data, recent designs also use split caches	Large Numbers(32-192) of General Purpose Registers with mostly split cache & instruction Cache
Clock Rate	33-50 MHz in 1992	50-150 MHz in 1993.
Cycles Per Instruction(CPI)	Between 2 & 15	One cycle for almost all instructions & an average CPI<1.5
CPU Control	Most microcoded using Control Memory(ROM) but modern CISC also use Hardwired Control	Most Hardwired without Control Memory.
Example	INTEL i486,IBM 390	INTEL i860, SPARC.